LatticeMico32 is licensed under a free (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA, application-specific integrated circuit (ASIC), or software emulation, e.g., QEMU). It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice Semiconductor parts the LatticeMico32 was developed for. AMD PowerTune uses LatticeMico32.[1]
The CPU core and the development toolchain are available as source-code, allowing third parties to implement changes to the processor architecture.
Features
RISC load/store architecture
32-bit data path
32-bit fixed-size instructions (all instructions are 32 bits, including jump, call and branch instructions.)
32 general purpose registers (R0 is typically set to zero by convention, however R0 is a standard register and other values may be assigned to it if so desired.)
Up to 32 external interrupts
Configurable instruction set including user defined instructions
Optional configurable caches (direct-mapped or 2-way set-associative, with a variety of cache sizes and arrangements)